1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to filling narrow openings formed in a semiconductor device using by using an ion beam etching step.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
For many device technology generations, the gate electrode structures of most transistor elements has comprised silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate dielectric layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices have turned to gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths of 14-32 nm or even shorter, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate dielectric layer of an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate dielectric layer may include tantalum oxide (Ta2O5), strontium titanate (SrTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O5), hafnium silicates (HfSiOx), hafnium silicon oxynitrides (HfSiOxNy), and the like. Furthermore, one or more of a plurality of different non-polysilicon metal gate electrode materials may be used in HK/MG configurations so as to control the work function of the transistor, as will be discussed in more detail below. These metal gate electrode materials may include, for example, titanium nitride (TiN), titanium oxynitride (TiON), titanium oxycarbide (TiOC), titanium oxycarbonitride (TiOCN), titanium aluminum (TiAl) tantalum silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi), aluminum nitride (AlN), tungsten (W), molybdenum (Mo), hafnium nitride (HfN), hafnium silicide (HfSi), titanium (Ti), aluminum (Al), platinum (Pt), rubidium (Ru), iridium (Ir) and the like.
One processing method that has been used for forming high-k/metal gate transistor elements is the so-called “gate last” or “replacement gate” technique. FIGS. 1a-1e depict one illustrative prior art method for forming an HK/MG gate electrode structure based on the replacement gate technique, which will now be described in further detail.
FIG. 1a schematically shows a cross-sectional view of an illustrative semiconductor device 100 comprising a substrate 101, in and above which an illustrative transistor element 150 may be formed based on well-established semiconductor device processing techniques. The illustrative transistor element 150 may include a gate electrode structure 110, and the substrate 101 may represent any appropriate substrate on which may be formed a semiconductor layer 103, such as a silicon-based layer, or any other appropriate semiconductor material that facilitates the formation of the illustrative MOS transistor element 150. It should be appreciated that the semiconductor layer 103, even if provided as a silicon-based layer, may include other materials, such as germanium, carbon and the like, in addition to an appropriate dopant species for establishing the requisite conductivity type in an active region 102 of the semiconductor layer 103. Furthermore, in some illustrative embodiments, the transistor element 150 may be formed as one of a plurality of bulk transistors, i.e., the semiconductor layer 103 may be formed on or be part of a substantially crystalline substrate material, while in other cases specific device regions of the device 100 or the entire device 100 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided below the semiconductor layer 103.
As shown in FIG. 1a, the active region 102 is typically enclosed by an isolation structure 104, which in the present example may be provided in the form of a shallow trench isolation that is typically used for sophisticated integrated circuits. In the illustrated embodiment, highly doped source and drain regions 106, including extension regions 105 that usually comprise a dopant concentration less than the highly doped regions 106, are formed in the active region 102. The source and drain regions 106, including the extension regions 105, are laterally separated by a channel region 107. Furthermore, the source and drain regions 106 may also comprise metal silicide contact regions 116, which may facilitate the formation of electrical contacts to the transistor element 150. The gate electrode structure 110 is formed above the channel region 107 and may be made up of a gate insulation layer 108, which electrically and physically isolates a dummy gate electrode 109 from the underlying channel region 107, as well as sidewall spacer structures 110s formed on the sidewalls of the dummy gate electrode 109. Depending on the device requirements and/or the process strategy, the sidewall spacer structures 110s may include two or even more spacer elements, such as offset spacers, conformal liners, and the like, which may act as appropriate implantation masks for creating the lateral dopant profile for the highly doped drain and source regions 106 and extension regions 105.
In the HK/MG replacement gate technique, the gate insulation layer 108 may be made up of a high-k dielectric material such as tantalum oxide, strontium titanium oxide, hafnium oxide, hafnium silicate, zirconium oxide and the like, and the dummy gate electrode 109 may comprise, for example, polysilicon. Furthermore, in some embodiments, an ultrathin interfacial layer (not shown) may be present above the active region 102, between the gate insulation layer 108 and the underlying channel region 107. Depending on the device requirements, the ultrathin interfacial layer may comprise a silicon-based dielectric material, such as silicon dioxide, silicon oxynitride and the like, and may have a thickness of approximately 0.1-0.8 nm, whereas in specific embodiments the ultrathin interfacial layer may be approximately 0.3-0.5 nm.
As illustrated in FIG. 1a, the semiconductor device 100 may also comprise an interlayer dielectric material layer 111, which may act to electrically isolate the transistor element 150 from any subsequently formed metallization layers (not shown). The interlayer dielectric material layer 111 may in some embodiments comprise silicon dioxide, silicon nitride, silicon oxynitride, and the like, or a combination of these commonly used dielectric materials. Depending on the device design and overall process flow requirements, the interlayer dielectric material layer 111 may also comprise suitably selected low-k dielectric materials, such as porous silicon dioxide, organic polyimides, or organosilicates such as methyl silsesquioxane (MSQ) and the like.
FIG. 1b shows the illustrative prior art semiconductor device 100 of FIG. 1a in a further advanced stage of manufacturing, wherein the dummy gate electrode 109 may be removed in preparation for forming a replacement metal gate electrode. As shown in FIG. 1b, an etching process 131 may be performed to form an opening 112 in the interlayer dielectric material 111. In certain embodiments, the etching process 131 may be designed to selectively remove the material of the dummy gate electrode 109 relative to the material composition of the interlayer dielectric material layer 111 and the gate insulation layer 108. For example, a dummy gate electrode 109 comprising polysilicon material may be selectively removed using any one of several suitably designed wet etch chemistries well known in the art—such as wet inorganic ammonia, tetramethylammonium hydroxide (TMAH), and the like—without inducing undue damage to the surrounding materials, including the nitride and/or oxide material comprising the interlayer dielectric material layer 111, the sidewall spacer structures 110s, the high-k dielectric material comprising the gate insulation layer 108, the ultrathin interfacial layer (not shown), or the channel region 107. Additionally, well known dry etch recipes, such as fluorine or halogen-based RIE and the like, may also be used.
In a typical replacement metal gate (RMG) process flow, multiple layers of metal fill material may be formed in the opening 112 so as to thereby form a replacement metal gate electrode 129 (see FIG. 1e). Depending on the overall device requirements, the multiple material layers may be required so as to facilitate the proper control of the device work function, both for P-type and N-type MOS (i.e., PMOS and NMOS) transistor elements. For example, the work function of an illustrative NMOS transistor element may, in certain illustrative embodiments, require forming an N-metal in a multi-layer metal stack, which may comprise, for example, Ti, Al, TiAl, HfN, HfSi, HfSiN, and/or TaC. In some illustrative embodiments of the present disclosure, the N-metal may be remote from the high-k dielectric material gate insulation layer 108—i.e., wherein other material layers intervene therebetween—such as a high-k dielectric/TiN/N-metal/TiN/Ti/Al stack configuration. In other illustrative embodiments, the N-metal may be in direct contact with the high-k dielectric material gate insulation layer 108—i.e., a stack configuration such as high-k dielectric/N-metal/TiN/Ti/Al.
On the other hand, the work function of an illustrative PMOS transistor element may, in some embodiments, require forming a P-metal in a multi-layer metal stack, which may comprise, for example, TiN, TiON, TiOC, TiOCN, Pt, Ru, and/or Ir. In certain illustrative embodiments, the P-metal may be in direct contact with the high-k dielectric material gate insulation layer 108—i.e., a stack configuration such as high-k dielectric/P-metal/TaN/TiN/Ti/Al. In other illustrative embodiments, the P-metal may be remote from the high-k dielectric material gate insulation layer 108—i.e., with other material layers intervening therebetween—such as a high-k dielectric/TiN/TaN/P-metal/Ti/Al stack configuration. Other suitable combinations of metal gate material layers may also be used, depending on the specific type of MOS transistor and the desired work function.
FIG. 1c depicts the prior art semiconductor device 100 of FIG. 1b in an advanced manufacturing stage, wherein a first layer of metal fill material 121 of the replacement metal gate electrode 129 (see FIG. 1e) may be formed above the device 100. As shown in FIG. 1c, a first conformal deposition process 132, such as, for example, an atomic layer deposition (ALD), a chemical vapor deposition (CVD), or a physical vapor deposition (PVD) process and the like, may be performed to deposit the first layer of metal fill material 121 above the upper surface 111s of the interlayer dielectric material layer 111 and the inside of the opening 112. Depending on the overall device requirements and MOS transistor type, as well as, in some cases, the specific high-k dielectric material comprising the gate insulation layer 108, the first layer of metal fill material 121 may comprise an appropriately selected metal gate fill material such as titanium, titanium nitride, titanium oxynitride, and the like. Furthermore, as noted above, the work function of the transistor element 150 may also be affected by the thickness of the first layer of metal fill material 121, which may, in some embodiments, range from 1-2 nm.
While the ultimate goal of a conformal deposition process may generally be to form a material layer having a highly uniform thickness, some degree of deposition non-conformality may occur. More specifically, the actual as-deposited thickness of the first layer of metal fill material 121 may vary from point to point along the inside surface 112s of the opening 112, as well as along the upper surface 111s of the interlayer dielectric material layer 111, depending on the specific deposition parameters used to perform the first conformal deposition process 132. For example, as shown in FIG. 1c, the thickness of the first layer of metal fill material 121 may be somewhat increased proximate to and around the upper corner 113 of the opening 112, thereby resulting in a reduced opening size 113d of the opening 112 proximate the upper corner 113 when compared to the opening size 112d proximate the bottom 112b of the opening 112. Additionally, the degree to which the reduced opening size 113d differs from the opening size 112d may vary depending on the specific type of conformal deposition process used to form the first layer of metal fill material 121 (i.e., ALD, CVD, PVD, etc.).
FIG. 1d shows the illustrative prior art semiconductor device 100 of FIG. 1c after a second layer of metal fill material 122 has been formed above the first layer of metal fill material 121 of the device 100. For example, the second layer of metal fill material 122 may be deposited above the first layer of metal fill material 121 based on a second conformal deposition process 133, such as ALD, CVD, PVD and the like. Depending on the specific work function control parameters for the transistor element 150, the specific type of conformal deposition process used to form the second layer of metal fill material 122 may either be the same as, or different than, the type of process used to form the first layer of metal fill material 121. For example, in some embodiments, both first and second conformal deposition processes 132, 133 may be an ALD process, whereas in other embodiments, the first process 132 may be an ALD process and the second process 133 may be a CVD process or a PVD process. In yet other embodiments, the first and second conformal deposition processes 132, 133 may both be CVD process, or the first process 132 may a PVD process and the second process 133 may be an ALD process. Depending on the overall device and/or work function control requirements, other combinations of metal deposition processes may also be performed.
As noted previously, both the thickness of and the material comprising the second layer of metal fill material 122 may be adjusted so as to control the work function of the transistor element 150. Depending on the overall device requirements, the second layer of metal fill material 122 may be deposited to a thickness of 1-2 nm, and may comprise a material that is different from the material comprising the first layer of metal fill material 121. For example, as discussed previously, in illustrative embodiments of the present disclosure wherein the first layer of metal fill material 121 comprises titanium nitride (TiN), the second layer of metal fill material 122 of an NMOS transistor may comprise titanium aluminum (TiAl), whereas the second layer of metal fill material 122 of a PMOS transistor may comprise tantalum nitride (TaN). Other material combinations may also be used, depending on the desired work function and overall device requirements.
As with the first layer of metal fill material 121, the second layer of metal fill material 122 may also exhibit, to some degree, an amount of deposition non-conformality proximate the upper corner 113 of the opening 112, as illustrated in FIG. 1d. That is, the thickness of the second layer of metal fill material 122 may, in some cases, be greater proximate the upper corner 113 of the opening 112 than proximate the bottom 112b of the opening 112, thereby further reducing the opening size 113d when compared to the opening size 112d. 
FIG. 1 e shows the prior art semiconductor device 100 of FIG. 1d during a further manufacturing stage, wherein a the replacement metal gate electrode 129 has been substantially completed. As shown in FIG. 1e, a third layer of metal fill material 123 may be formed above the second layer of metal fill material 122 of the semiconductor device 100 so as to fill the remaining space inside of the opening 112. In some embodiments, the third layer of metal fill material 123 may be formed above the second layer of metal fill material 122 using one of several suitably designed conformal deposition processes, such as ALD, CVD, PVD, and the like. Furthermore, depending on the device requirements and the desired work function of the transistor element 150, the material comprising the third layer of metal fill material 123 may comprise a suitable metal gate material, such as, for example, titanium nitride (TiN), hafnium nitride (HfN), hafnium silicide (HfSi), titanium oxynitride (TiON) and the like. Thereafter, a planarization process (not shown) may be performed to remove excess material of the first, second and third layers of metal fill material 121, 122, 123 that may have been formed above the upper surface of the interlayer dielectric material layer 111, thereby forming the replacement metal gate electrode 129 in the opening 112. Depending on the desired process strategy, as well as the materials comprising the first, second and third layers of metal fill material 121, 122, 123, the planarization process may comprise, for example, a chemical mechanical polishing (CMP) process, or a suitably designed wet or dry selective etch process, recipes for which are well known in the art.
Depending on the deposition parameters employed during the conformal deposition process used to form the third layer of metal fill material 123, the increased thickness of the second layer of metal fill material 122 proximate the upper corner 113 of the opening 112 and the commensurately reduced opening size 113d (see FIG. 1d) may prevent the third layer of metal fill material 123 from completely filling the opening 112, thereby leaving an unfilled void space 114 in the replacement metal gate electrode 129, as shown in FIG. 1e. The problem of incomplete filling of the opening 112 is of particular importance in later generation technology nodes, as the gate lengths of transistor elements—and the opening sizes available in the RMG processes—continue to shrink. For example, in the 22/20 technology node, where the gate length and/or opening size may be on the order of 25-28 nm or even less, a conformally deposited first layer of metal fill material 121 having a nominal thickness of 1-2 nm may result in a reduced opening size 113d proximate the upper corner of the opening of approximately 12-15 nm. This leaves a significantly reduced opening size through which to form the second and succeeding layers of metal fill material, thereby leading to a reduced ability to control the transistor's work function, and an associated reduction in overall device reliability and product yield.
Accordingly, there is a need to implement new design strategies to address the manufacturing and performance issues associated with the typical replacement metal process flows utilizing multilayer metal fill regimes for aggressively scaled transistor elements. The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.